1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to an improved dry etch method of use in the formation of ultra thin spacers.
2. Description of the Related Art
Fabrication of a metal oxide semiconductor field-effect transistor (MOSFET) device is well known. MOSFETs are generally manufactured by placing an undoped polycrystalline silicon ("polysilicon") material over a relatively thin layer of silicon dioxide ("oxide"). The polysilicon material and the oxide are then patterned to form a gate conductor arranged upon a gate oxide with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species.
Operating transistors which have heavily doped source/drain regions arranged directly adjacent to the gate conductor often experience a problem known as hot carrier injection ("HCI"). HCI is a phenomena by which the kinetic energy of the charged carriers (holes or electrons) is increased as they are accelerated through large potential gradients, causing the charged carriers to become injected into and trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field ("Em") occurs near the drain during saturated operation. Because of carrier entrapment within the gate oxide, a net negative charge density forms in the gate oxide. The trapped charge can accumulate with time, resulting in a positive threshold shift in a NMOS transistor, or a negative threshold shift in a PMOS transistor.
To overcome problems of sub-threshold current and threshold shift resulting from HCI, an alternative drain structure known as the lightly doped drain ("LDD") is commonly used. The purpose of the LDD is to absorb some of the potential into the drain and thus reduce Em. A conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier dopant self-aligned to the gate conductor on which two sidewall spacers have been formed. The purpose of the first implant dose is to produce a lightly doped section within the active area (hereinafter "junction") at the gate edge near the channel. The second implant dose is used to form a heavily doped source/drain region within the junction laterally outside the LDD area. Because the second implant dose is spaced from the channel by the spacers, the lateral thickness of the spacers dictates the thickness of the LDD and source/drain regions.
The spacers are typically formed by first chemical vapor depositing ("CVD") an oxide layer over the gate conductor. The oxide layer is then patterned to form spacers on the sidewalls of the gate conductor. Since the oxide layer is conformally deposited over the gate conductor, and thus is thicker at the edges of the gate-to-junction step then on flat (horizontal) areas, an anisotropic etch process will clear oxide from the flat areas while leaving spacers on the side walls of the gate electrode. Because of the ability of dry etch processes to etch anisotropically (in comparison to wet etch processes, which etch isotropically), dry etching is typically used in spacer formation.
There are three types of dry etching processes: those that have a physical basis (e.g., ion beam milling), those that have a chemical basis (e.g., plasma etching), and those that combine both physical and chemical mechanisms (e.g., reactive ion etching). Primarily physical dry etch methods may not exhibit sufficient selectivity to both masking materials and the underlying substrate, while primarily chemical processes typically etch isotropically. Consequently, ion-assisted etching processes that combine the two mechanisms are often preferred in spacer fabrication.
Ion assisted etching can be carried out in a variety of types of commercial dry etch systems. One commonly used configuration is the parallel electrode reactor system. These systems typically have a diode configuration with two parallel, circular electrodes spaced by a gap. One of the electrodes is connected to a radio frequency (RF) power supply, and the other is grounded. The wafer is placed on the to-be-powered electrode. A pump is used to adjust the pressure within the reaction chamber to the desired level, and extant gases are introduced into the reaction chamber. By applying power to an electrode, a plasma may be created within the chamber. Because the wafer is placed on the powered electrode, energized ions from the plasma may bombard the wafer. The combination of physical and chemical processes allows for etching that is both anisotropic and selective. The degree of anisotropy and selectivity, as well as other factors such as the etch rate, are determined by a variety of parameters. These parameters include: the quantity and frequency of the power supplied, the gap between the electrodes, the type and flow rate of extant gas into the reaction chamber, and the pressure within the reaction chamber.
The values of the above-listed parameters selected for a particular etching process can have a significant impact on the properties of the final integrated circuit. Therefore, these values must be carefully selected. Because of the effect that the width of the LDD and source/drain regions has on circuit attributes (e.g., drive current), it is important that the thickness of these regions be as close to the desired values as possible. Consequently, the dry etch processes used in the fabrication of sidewall spacers should result in the formation of spacers that have a high degree of thickness uniformity. That is, the thickness of sidewall spacers should vary as little as possible from desired values. Spacer thickness uniformity should occur both across each wafer and from wafer-to-wafer.
One measure of spacer thickness uniformity is the standard deviation of the thicknesses of a number of spacers. Standard deviation is a measure of the dispersion of a set of data from their mean, and may be calculated by taking the square root of the variance. By looking at the standard deviation of the thicknesses of a set of spacers formed by a particular etch process, the ability of that process to form uniformly thick spacers may be seen. Unfortunately, most conventional etch processes are only capable of forming spacers whose thicknesses have a standard deviation of 25 angstroms or greater. These variations in thickness can translate into deviations in LDD and source/drain width that deleteriously effect circuit performance. In addition, as feature size decreases the thickness of the spacers should also decrease as well. Because reduced feature sizes exacerbate the effect of a specific amount of deviation from average, the variability in spacer thickness uniformity that may result from conventional dry etch processes becomes an even greater problem when ultra thin spacers must be formed. Therefore, it is desirable to develop a method that would allow the formation of spacers with a higher degree of thickness uniformity than is possible with current etch techniques.